An analog-to-digital converter (ADC) is an interface between the analog domain and the digital domain. Several different ADC architectures exist. The successive approximation (SAR) ADC and pipelined ADC architectures can be combined to form an ADC architecture with relatively high conversion rate and relatively high resolution, e.g. with 10 or more effective number of bits (ENOB). A SAR ADC can be implemented using so called charge redistribution with a capacitive array and this scheme also generates a residue, the analog remainder part after conversion to a given number of bits. In a pipelined ADC, this residue is in turn input to a subsequent ADC stage.
Normally, there is an overlap, or redundancy, between the conversion ranges of two subsequent ADC stages in a pipelined ADC. For example, in a two stage pipelined ADC having a first ADC stage (or sub ADC) and a second, subsequent, ADC stage (or sub ADC), there is normally an overlap, between the least significant bit (LSB) of the first ADC stage and the most significant bit (MSB) of the second ADC stage. For example, if the first ADC stage has B1bits and the second ADC stage has B2bits, the total number of bits of the pipelined ADC is B=B1+B2-1, where the term−1is due to the overlap. Implementation of a pipelined SAR ADC is e.g. discussed in F. van der Goes et al., “A 1.5 mW 68 dB SNDR 80 Ms/s 2× Interleaved Pipelined SAR ADC in 28 nm CMOS,” in IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp. 2835-2845, December 2014.